As is known in this specific technical field, a synchronization process is used to recover a correct sampling phase and frequency in each communication system where a synchronous detection is performed. For instance, in hard disk drive applications the timing recovery is accomplished by splitting the process in two main stages, a first stage called “acquisition” and a second stage called “tracking”.
In the first acquisition stage, a known pattern, rich in timing information and called the “preamble”, generates a periodic signal. The recovery process of phase, frequency and gain may be started given that the expected readback waveform is known beforehand. In the second tracking stage the header is followed by the information content, that is unknown. Once this data is detected, the loops can rely on the estimated bits to compensate for the distortions on the readback signal.
The structure of a data sector is depicted in FIG. 1, wherein the information part, indicated by “data”, is sandwiched between additional fields. Each data sector may include the following fields. 4T Preamble: repetitive signal of period 4T, obtained by writing several times the sequence “1100” (where 1 and 0 refer the two media magnetization states), this preamble is needed to start both amplitude and synchronization recovery. Sync mark: which is a field indicating the start of user data. Data: which is an information field, generally protected by error correction codes with high rate and information part equal to the current standard for the operating system (e.g. 512 user symbols of 8 bits per symbol). Pad: is an additional field for flushing the data through the pipeline and for separating the sectors from each other.
A second order PLL is generally implemented in the HDD industry, such that it's possible to recover phase and frequency sampling errors. Two main approaches are adopted in the current techniques. One approach includes tracking the synchronization error via a PLL that controls the analog to digital converter, such that the readback signal is synchronously sampled respect to the written information. Another approach includes recovering the synchronization errors in the reading chain with a digital second order PLL, via a digital filter that works as phase interpolator.
For both techniques a critical parameter is the latency of the loop. Any loop delay will affect loop performance, and in particular the maximum acquisition speed that does not jeopardize PLL stability. High delays narrow the PLL stability region, forcing usage of longer settling times and thus reducing the format efficiency. In this respect, reference is made to the article by J. W. M. Bergmans: “Effect of loop delay on stability of discrete-time PLL,” IEEE Trans. Circuits Syst. I, vol. 42, pp. 229-231, April 1995.
The preamble length is determined by testing the acquisition response under a set of operating conditions with a known statistical distribution. The goal is to minimize the probability of either not acquiring properly or loosing timing lock over the frame because of poor timing identification over the header (preamble) field. This event is customarily denoted as ‘loss of lock’ (LOL).
From basic PLL theory, the LOL likelihood decreases with increasing preamble length. On the other hand the longer the preamble, the smaller the disk surface available for user data. The complex loop structure needed to perform a reliable synchronization estimate in poor signal-to-noise (SNR) conditions is implemented with difficulty at the required data rates in an HDD system, and latency is generally sacrificed to system reliability.
As loop latency is increased, more preamble is necessary in the acquisition phase to result in a loss of lock probability comparable with the sector retry rate. The first approach becomes critical if the equalization process is not closed in the analog domain, before the ADC converter. A criterion in choosing the equalizer structure is flexibility to enable the read path to adapt to widely different application scenarios. Choosing a digital finite-impulse-response (FIR) structure is generally preferable for implementation area, speed and technological reasons.
The delay in FIR outputs calculation contributes to the timing loop latency using the first approach, while it doesn't affect the other approach. In FIG. 2 the first approach is depicted. ADC is the analog to digital converter, FIR is the digital finite impulse response filter for equalizing, PD denotes the phase detector, LF the second order proportional-integrative loop filter, Acc is an integrator, while the complex of PLL and Mux/Phase Interpolator moves the sampling period of the analog to digital converter ADC.
In FIG. 3 the second approach is depicted. The same components of the previous approach are shown in the same positions. Differently from the first approach, in this approach a digital phase interpolation is performed via FIR filtering. It is noted that in FIG. 3 the FIR filter can still be moved inside the timing recovery loop.
FIG. 4 shows an alternative approach, know as “Tintoretto”, for timing loop recovery in current HDD Read/Write channels. This approach is an improvement of the above second approach. Since the writing and reading clocks are not synchronous to each other, the frequency difference needs to be compensated. As data stream is sampled with a fixed clock, it is necessary to build a continuous flux of samples, eventually destroying redundant samples (oversampling exception) or interpolating additional samples (undersampling exception).
In the approach shown in FIG. 4, a dynamic buffer is provided at the phase interpolator output. The average throughput at the dynamic buffer input is at the ADC frequency, while the output throughput is uniform at the write clock frequency.
Again, in the acquisition phase, the pattern is known beforehand: a monochromatic replica of the equalized and timing error free preamble pattern is generated as reference for the phase detector input (Preamble Generator). In tracking, the information bits are detected by a reduced complexity Viterbi detector. Different loop gains are implemented, with the purpose of increasing the loop bandwidth in acquisition (reduced latency) with respect to tracking (longer latency). While being advantageous in many aspects, this last approach still has a relatively long latency loop in the acquisition phase.